Perl, Pcie, Ethernet, Shell scripting, Python, CHI, Ace, USB 3.x, RISC-V, Uvm, Assertions, systemverilog, Axi, USB4, CXL, DDR5, DDR4, SVA

Perl, automation, Python, waveform viewers, coverage collection, verification methodologies, Uvm, systemverilog, Simulators, object-oriented design, gate level simulations, dpi

Verilog, VMM, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, systemverilog

Usb, Pcie, Test Plans, Verification environments, Regression management, SoC ASIC Verification, Waveform tools, Uvm, systemverilog, Coverage-driven verification, RTL design concepts, Axi, Test benches, APB, AHB

Unix, Bash, Svn, Git, Linux, Python, Tcl, Gate-Level Simulation, MBIST, Siemens Tessent, Test Access Networks, DFT Design Verification, ATPG, Scan Compression, Scan Architectures

Jtag, Perl, Verilog, Python, System Verilog, Tcl, Mentor Questa, Cadence Xcelium, Uvm, Synopsys VCS, APB, CRI, IJTAG, mixed signal verification

Computer Architecture, C, Gdb, Data Structures, Object Oriented Programming, Stl, Pli, Linux, Perl, Verilog, System Verilog, Uvm, System C, DV, dpi

Perl, Verilog, Python, SV, Cadence or equivalent simulation tools, SV scripting languages