static timing analysis, EDA tools for synthesis, VHDL, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, low-power design techniques, digital IC ASIC design, RTL quality tools such as Spyglass Lint CDC RDC

Dft, Physical and formal Verification, exposure to frontend and Analog processes, backend flows for MCU or low-power SoC designs

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

static timing analysis, LINT, Logic Synthesis, Dft, cdc, formal verification, Cadence-based ASIC design environments, low-power design methodologies, micro-architecture development, SystemVerilog RTL design

static timing analysis, Dft, low-power design methodologies, LINT, Cadence-based ASIC design environments, micro-architecture development, SystemVerilog RTL design, formal verification, Logic Synthesis, cdc

Programming and scripting languages, Nvme, Pcie, Test Plan Creation, Automation Frameworks, Verification and validation methodologies, Debugging and problem-solving skills, Testbench architecture, System Design of SSD, Simulation and emulation environments, NAND

Tcl, Vcs, Python, Perl, Version Control, assertion-based verification, Questa, Uvm, verification methodologies, systemverilog, CI CD, RTL simulation, functional coverage

Embedded Systems Development, Python Programming, Agile Development Methodologies, NAND flash memory design, Operating systems and system level concepts, SSD HDD storage systems, Software development verification, System failure analysis

Pre-silicon verification (UVM, coverage analysis), Protocol knowledge (PCIe, DDR), Ethernet, Usb, SoC/IP verification, Verification Tools