AI ML accelerators, systemverilog, vector processing units, functional coverage

Perl, Pcie, Ethernet, Shell scripting, Python, CHI, Ace, USB 3.x, RISC-V, Uvm, Assertions, systemverilog, Axi, USB4, CXL, DDR5, DDR4, SVA

Perl, automation, Python, waveform viewers, coverage collection, verification methodologies, Uvm, systemverilog, Simulators, object-oriented design, gate level simulations, dpi

Verilog, VMM, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, systemverilog

Jtag, Perl, Verilog, Python, System Verilog, Tcl, Mentor Questa, Cadence Xcelium, Uvm, Synopsys VCS, APB, CRI, IJTAG, mixed signal verification

Shell, Perl, Vcs, Python, Xcelium, Questa, Uvm, systemverilog, SVA

Verilog, VHDL, simulation debugging, DO-254, traceability validation methodologies, coverage-driven verification, systemverilog

Verilog, random stimulus, VMM, assertion-based verification, Uvm, systemverilog, functional coverage, advanced verification methodologies