Senior Design Verification Engineer

Job description

Job Role: Senior Design Verification Engineer

Exp: 4 - 8 years

Notice Period: Immediate

Location: Bangalore

 Key Responsibilities: 

• Develop and execute verification plans for complex digital designs 
• Create and maintain testbenches using System Verilog and UVM 
• Develop directed and constrained-random test cases 
• Perform functional, code, and assertion coverage analysis 
• Debug RTL, testbench, and simulation issues 
• Work closely with Design, Architecture, and Physical Design teams to ensure first-pass silicon success 
• Participate in reviews of specifications, verification plans, and test environments 

Required Skills: 

• 4+ years of experience in ASIC/SoC Design Verification 
• Strong hands-on experience in SystemVerilog and UVM 
• Experience with verification methodologies, coverage-driven verification, and assertions (SVA) 
• Good understanding of digital design concepts and computer architecture 
• Experience with industry-standard simulators (VCS, Xcelium, Questa, etc.) 
• Strong debugging and problem-solving skills 

Preferred: 

•  Experience in verifying protocols such as AMBA (AXI/AHB/APB), PCIe, USB, Ethernet, DDR, or similar 
•  Exposure to scripting languages such as Python, Perl, or Shell 

Interested can share Resume to [Confidential Information]