synopsys primetime , Tcl Scripting, PnR flow Floorplan Placement CTS Routing, SDC STA concepts timing constraints, Cadence Tempus

PERL, Python, Tcl, Synthesis, Cadence

Timing Analysis, RTL to Netlist Logical equivalence check, Digital Synthesis, Timing constraint development, STA flow setup, EM IR flows, DFT insertion, Physical Verification, Timing Noise DRC, Signoff checks

rc extraction , C, Unix Shell, routing, PERL, Linux, Tcl, functional ECOs, Physical Design Flow, floorplanning, cross talk, timing optimization, low power implementation methods, Power Planning, Signal Integrity, formal verification, debugging timing violations, delay analysis, Placement, IR drop analysis, Clock Tree Synthesis

synopsys primetime , Debugging, Python, Perl, Tcl, OCV, timing closure techniques, latency, multicycle paths, derates, MMMC concepts, SDC timing exceptions, timing constraints development, POCV, ECO methodologies, clock uncertainty, Case Analysis, setup hold analysis, Cadence Tempus, clock tree, path-based analysis, jitter, false paths, Timing Closure, AOCV, skew

Sta, LINT, Synthesis, cdc, Dft, MMMC, primetime, Tempus, SDF generation, ETM Timing model generation

RTL2GDS, STA convergence, Synopsys, EDA Tools, Physical Design, Synopsis Primetime, Cadence

Tcl, Python, Perl, RTL to GDSII, LVF POCV variation formats, Constraint Generation, STA Static Timing Analysis, Cadence Tools, Tweaker Prime Time, Automation scripts, Timing ECO Implementation, Timing Closure, Timing Analysis, Digital design Implementation

Python, Tcl, Cadence Innovus, Logic Synthesis, Setup Hold analysis, Cadence Genus, Cadence Tempus