Hard Macros (SerDes), Flip-Chip, PNR, Cadence Tools, Physical Implementation, FDSOI 22nm

layout verification , static timing analysis, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, SoC designs, physical design implementation, Power Clock Distribution, structural design checking, Place And Route, power and noise analysis, RTL to GDS, Floor Planning, static and dynamic power integrity, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis