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Showing 9 jobs
Skills:
cache coherency , rtl development , Verilog, System Verilog, VHDL, design verification strategy, memory consistency, micro-architecture, Functional Verification
Skills:
Perl, Verilog, Python, Tcl, microarchitecture development, Synthesis, cdc, systemverilog, Rtl Design, RDC, EDA Tools, LINT, low-power methodologies, STA concepts
Skills:
MATLAB, Verilog, Python, PSK, BCH, RF Systems, LDPC, SDR Architectures, ADC DAC architectures, DSP Algorithms, FPGA Development, VHDL, Vivado, DVB-S2, JESD204B C, DVB-S2X, Xilinx, QPSK, Rtl Design
Skills:
PERL, Verilog, Static Timing Analysis, Python, Ethernet, Tcl, LINT, ASIC Synthesis, cdc, AMBA Bus, SoC integration, Synopsys toolsets, Rtl Design, VHDL, equivalency checking, HBM, ARM core-based designs, PCIe Gen5, USB4.x, UCIe, FPGA prototyping, Axi, APB, FPGA based designs, AHB, ip development
Skills:
Dsp, C, Debugging, Verilog, System Verilog, Systemc, Gate-Level Simulation, Power aware verification, Uvm, Assertions, Asic Design Verification, NPU, Processor Architecture, formal verification, HVL, Digital Design, Assembly
Skills:
Verilog, Cache, Soc Architecture, fabric coherence, memory compression, systemverilog, logic synthesis techniques, FPGA and emulation platforms, digital logic design principles, Synthesis, DRAM, FPGA design verification, assertion-based formal verification, RTL design concepts, Dft, low-power design techniques, power analysis
Skills:
Area and power-efficient complex RTL design, High performance low latency high bandwidth design techniques, Low power microarchitecture techniques, Experience with simulators and waveform debug tools, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications
Skills:
Unix, Ruby, perl, Tcl, Linux, Computer Architecture, interconnects, high speed IO controller design, ASIC Design, Design Verification, front-end EDA tools, Verilog Hdl, floor-planning, Synthesis, Timing Closure, post-silicon validation, power intent
Skills:
Unix, Usb, DDR, Perl, Linux, Pcie, Ethernet, Sata, Ruby, Tcl, Verilog Hdl, ASIC Design, high speed IO controller design, front-end EDA tools
