power optimization , C, Linux, Perl, Unix Shell, Tcl, Advanced STA Concepts, Physical Design Flow, Block level PnR convergence, Timing Convergence, Cadence Innovus, LVS, PTSI Tempus, Physical Verification, formal verification, Timing Closure, DRC, PDN, Floor-planning, Place And Route, Synopsys ICC2

redhawk , Scripting Languages, Python, Perl, Tcl, power analysis, primetime, PrimeClouser, Tempus, Cadence Innovus, manufacturing sign-off, DFT insertion, Voltus, ASIC SoC physical design, Calibre, EDA Tools, low-power design, EM IR analysis, advanced nodes, multi-clock domain handling, Timing Analysis, Physical Verification, reliability checks, Signal Integrity

Tcl Scripting, Static timing Analysis, Cadence Tools, Synthesis, Physical Design, Physical Verification, Backend flows, Clock Tree Synthesis, Place Route Reliability

Routing, Python, Physical Design, Timing Closure, RTL

Computer Architecture, Scripting Languages, Physical Design

python, perl, Physical Design