Batch Apex, Flows, Triggers, Jenkins, Devops, Git, Hl7, APEX, Azure DevOps, Salesforce APIs, Salesforce Health Cloud, SOAP APIs, FHIR, Copado

Mentor, Uvm, firmware interaction, Synopsys, AMs, systemverilog, Cadence, Siemens, Calibration and link training flows, Register models, industry VIPs, Avery, SERDES

Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Mentor, Cadence, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis

Javascript, CSS, Visualforce, Saml, APEX, Rest Apis, HTML, Salesforce Service Cloud, Salesforce DX, OIDC

Process Builder, APEX, Soql, Visualforce, Salesforce Cpq, Git, Sales Cloud, Service Cloud, Salesforce Flows, Flosum, Copado, Change Sets

CSS, HTML, Javascript, Azure DevOps, SFDX, Email-to-Case, Web-to-Case, Salesforce Service Cloud, Lightning LWC, Lightning Flows, CICD tools, SOAP APIs, Salesforce Apex, Web Components

memory controllers , Verilog, Flash, Ddr3, Sta, CHI, Memory, clocking system modes, Rtl Design, Security, physically aware design flows, power management, LPDDR, Bunch-of-wires, Synthesis, multi-clock domain architectures, power optimization techniques, Debug, D2D protocols, UCIe, systemverilog, Rom, Axi, Timing Closure, low-power design techniques, AHB, Ram