Perl, Verilog, Python, Tcl, Synopsys VCS, Mentor Questa, VHDL, Cadence Xcelium, Uvm, systemverilog

Perl, Python, constraint-random tests, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog

SV, Uvm, PSS

Python, Perl, Pcie, Uvm, JasperGold, LPDDR, VC Formal, CHI, Ace, GPUs, Verdi, Synopsys VCS, ARM CPU, Cadence Xcelium Simulator, DLA, HBM, Axi, Network on chip, AMBA protocols, ATB

Scripting (Perl/Python/Shell), SystemVerilog/UVM, DDR/LPDDR Protocols, Functional and Code Coverage, RTL Design and Debugging, Assertion-Based Verification, IP verification

Linux, Perl, C++, System Verilog, Firmware, Ip, Digital Design

functional and code coverage techniques, UVM methodology, systemverilog