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Showing 4 jobs
Skills:
Perl, Python, Tcl, ATE Functional CHAZ vector enablement, MBIST verification, SV, Functional vectors generation, SV UVM monitors, Uvm, SoC Verification, Test controller architecture
Skills:
Verilog or VHDL, Automated characterization flows, Digital and Mixed-signal designs, FPGA characterization
Skills:
Tcl, System Verilog, Python, Perl, Vcs, Questa, Uvm, Modelsim
Skills:
Cadence - Virtuoso, Tcl, Python, Perl, Spice Simulator, Synopsys, Uvm, SV, Mentor tools, Verilog-A, Verilog-D, Cadence, Verilog Hdl, Verilog-AMS, AMS simulation environment
