Debugging, Test Planning, Simulation, systemverilog, Uvm, IP verification, Testbench development, Verification architecture, Mentoring

Logic Design, DDR, AMS verification, system level design, Mixed Signal IP design, AMS design techniques, High-speed circuits, Lab debugs on AMS IPs, Tx Rx CTLE Amplifiers Samplers, Analog Mixed Signal design, HBM technologies, Circuit architecture, SERDES

Fcoe, Ethernet, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

testbench development, UVM methodology, test plan reviews, debugging complex IP designs, systemverilog

C, Shell, Verilog, Python, Tcl, Systemc, Test Planning, systemverilog, constrained-random verification, formal verification, power-aware verification, UVM-based testbench development, NoC bus and interconnect verification