Python, Artificial Intelligence, Digital, Synthesis, Physical Design, Electronics, Application Engineering, RTL, ASIC Design

routing, Perl, Python, Tcl, ASIC design flow, Synthesis, signoff, EDA Tools, Timing Closure, Placement, PPA optimization, RTL-to-GDSII

Verilog, ASIC design flows, AI-driven chip design, LLM technologies, Hardware Verification, systemverilog