Usb, Perl, Verilog, Sata, Python, VMM, PCI Express, Uvm, systemverilog

Jtag, Gpu, Soc, Dsp, C Shell, Tcl, System Verilog, Python, Perl, Uvm, Ip, Ai, AHB, APB, Axi, AMBA protocols

Usb, C, Debugging, Object Oriented Programming, Writing Test Cases, DDR, Ethernet, Perl, Pcie, Tcl, Function coverage, Coverage driven verification, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, Test bench development, CXL, Simulation, Eth

scoreboarding, memory controller architecture, AXI protocol, assertions SVA, Uvm, DDR protocol JEDEC specifications, functional coverage, GLS, systemverilog

Makefile, Octave, MATLAB, Digital Signal Processing, Scripting Languages, Perl, Python, functional code coverage analysis, UVM-based testbench infrastructure, HW emulation, FPGA prototyping, formal verification, functional cover point development, Power aware simulations, gate level simulations, APB protocol, IP and SoC level verification, assertion development

static timing analysis, circuit simulation with spice simulators, Gate level simulations with SDF back annotation, transient analysis, timing arcs, DC analysis, circuit characterization timing libraries, netlist simulation, Uvm, Verilog MOS switch level models, System Verilog Assertions

Uart, python, Debugging, SV, test cases coding, Uvm, Test bench development, IJTAG, APB, Code and Functional coverage analysis, Axi, BUS Protocols

arm architecture , C, Ethernet, Pcie, Usb, DDR, HBM, Uvm, SoC DV execution, assertion-based formal verification tools, TLMs in SystemC, hardware emulation support

Cadence - Virtuoso, Tcl, Python, Perl, Spice Simulator, Synopsys, Uvm, SV, Mentor tools, Verilog-A, Verilog-D, Cadence, Verilog Hdl, Verilog-AMS, AMS simulation environment