arm architecture , Axi, verification methodologies, APB, Uvm, verification tools for simulation and debug, AHB

DDR, Pcie, Perl, Python, Axi, Uvm, AHB, systemverilog, NAND, ASIC simulation tools

Vcs, Makefile, Shell, Perl, Python, Assertion-based verification, Xcelium, verification automation frameworks, Functional and code coverage closure, Formal verification tools and methodologies, PSL, Uvm, systemverilog, CI CD verification flows, simulation acceleration, Questa, high-speed interface protocols, Regression infrastructure, AI-assisted verification tools, Vivado Simulator, SVA, Coverage-driven verification strategies

C, HTML, Sql, Python, Scripting Languages

Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Verdi, IUS, UVM environments, SystemVerilog UVM, GLS, coverage closure, debug tools, testbench architecture, Axi, IP SOC verification, Questa, CXL, CPU-based verification

Verilog, formal verification, VHDL, Chisel, JasperGold, VC Formal, Object-oriented Programming, Formal Abstraction Techniques, systemverilog

Shell, C, Perl, Python, Tcl, Uvm, systemverilog

Ovm, Verilog, Database Management, Uvm, Synopsys VCS, Cadence IES, Cadence Jasper, Metric-driven verification, Regression management, Calibration board skew and jitter modeling, Verification techniques, Contention checking, silicon debug, Debug environments, Simulation Tools, Memory controller protocols, Power verification, Reset verification, Gate level simulation, Formal property checking tools, Verification management tools, Verification methodology, High speed interface verification

Linux, Perl, Python, Tcl, Synopsys Custom Compiler, Layout automation, VoltusXFA, Calibre, Skill, Totem, Physical Verification, Pulsic Unity Itools, PDN analysis tools, Cadence Virtuoso, ICV

Usb, C, C++, Debugging, Test Plan, Object Oriented Programming, Writing Test Cases, Oop, DDR, Ethernet, Pcie, Perl, Tcl, Function coverage, Coverage driven verification, Uvm, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, CXL, Test bench development, Simulation, System-Verilog