Mac, Pcie, Switch, 1G Ethernet, UFS, SV, XUSB, High Speed IO verification, verification tools for simulation and debug, Uvm

Dsp, Soc, C Shell, Gpu, Jtag, Perl, System Verilog, Python, Tcl, Ip, Ai, AMBA protocols, Uvm, Axi, APB, AHB

Verification technologies (Simulation, LRM), Synopsys EDA tools (VCS, Verdi), HDL languages (Verilog, VHDL), Tcl, Uvm, SVA, Digital design fundamentals, systemverilog, Scripting UNIX

Jtag, Pcie, Perl, System Verilog, Python, Tessent Embedded Analytics, UltraSoC, UVM methodology, Design for Debug, High speed USB, RISC Debug Architectures

Tcl Scripting, Ovm, Unix Shell Scripting, Perl, Verilog, Ethernet, System Verilog, CMOS logic design, IC chip design development flow process, Uvm, Circuit Analysis, CAE CAD tools, JESD, Axi, VHDL, AHB, Circuit Design, coverage assertion driven verification

simvision , Perl, Python, FineSim, Xcelium, UVM-based verification methodologies, WaveView, analog and mixed-signal circuits, DRAM memory architecture, systemverilog, SpectreFx, Hspice, PrimeSim, FastSpice tools, virtuoso