layout verification , Computer Engineering, System Verilog, Tcl, low-power designs, Electrical Engineering, Computer Science, Vlsi Design, design rules

Verilog, LINT, cdc, Micro-architecture development, Functional Safety concepts, systemverilog, Synthesis checks, RDC, ASIL requirements, RTL design and integration, ISO 26262, Safety analysis methodologies

Logic Design, Front-end design tools and methodologies, Synthesis, Static-timing closure, Custom SoC ASIC products, formal verification, Debug skills, Block-level function verification, Gate-level simulations, Micro-architecture, Rtl Design