Perl, Tcl, Full-custom memory layout development, EDA Tools, ERC, EMIR analysis, DRC, LVS, Cadence Virtuoso

static code analysis , Java, C, Gdb, Valgrind, Jtag, Uml, Enterprise Architect, Linux, Hypervisor, Rhapsody, Trace32, Qnx, Python, Inter Guest OS IPC, Adaptive Autosar, performance optimization, code coverage tools, Performance Analysis

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Perl, Python, Tcl, Physical verification and ECO implementation, primetime, Floorplanning and physical architecture, Tempus, Cadence Innovus, Timing closure and SI debugging, CTS and clock distribution optimization, IR EM and power integrity analysis, Synopsys ICC2

Prometheus, Bash, Grafana, Jira, Jenkins, Git, Confluence, Bitbucket, Perl, Openshift, Python, Kubernetes, GitOps, OpenShift pipelines, DevOps methodology, Tracing service mesh

PERL, Python, Tcl, Ir, Cadence, Mentor, LVS, EM Signoff, Synthesis, Formal Equivalence, DRC, Synopsys

redhawk , primetime, PDN methodology, floorplanning, physical design implementation, STA constraints, Tempus, Cadence Innovus, IR EM mitigation, Physical Verification, Voltus, signoff tools, Synopsys ICC2

network security, Network Protocols, Python, Bash, Cisco firewalls, vendor firewalls