Shell, Perl, Verilog, Python, Tcl, LINT, cdc, PCI Express PCIe Gen4 Gen5 Gen6, systemverilog, Timing-aware RTL Development, ASIC RTL Design, Synthesis, RDC, Digital Logic Implementation, Microarchitecture, SoC Integration

Verilog, Cache, Soc Architecture, fabric coherence, memory compression, systemverilog, logic synthesis techniques, FPGA and emulation platforms, digital logic design principles, Synthesis, DRAM, FPGA design verification, assertion-based formal verification, RTL design concepts, Dft, low-power design techniques, power analysis