Vcs, Verilog, Python, System Verilog, RTL Design Principles, Xcelium, Uvm

Vcs, Verilog, Python, System Verilog, RTL Design Principles, Xcelium, Uvm

System Verilog, MPHY, UFS, Unipro, Asic verification, Uvm

C, Nvme, JIRA, Jenkins, DDR, Shell, Pcie, Bitbucket, Perl, Ddr3, System Verilog, Python, use-case verification, coverage analysis, UVM environment development, gate-level simulation, UVM verification, AMBA AXI AHB APB protocol, post-silicon bring-up debug, functional test vector development, LPDDR, performance verification, Assembly

Asic, Vlsi Design, SoC Verification

code coverage , Fpga, Ovm, Test Cases, Hdl, Shell, Pcie, Verilog, Debugging, System Verilog, Python, Perl, Pci, Sta, test benches, RTL, Uvm, DDR PHY, Ethernet MAC, VHDL, ASIC, RTL top level integration, Functional coverage, Frontend Design, Logic Synthesis, HVL

Vcs, programming, System Verilog, Scripting, Python, Asic verification, NCSim, verification of HBM memory interfaces, UVM testbench development, verification of SerDes IP block interfaces, Modelsim, formal model equivalence checking

SystemVerilog Assertions, Uvm, systemverilog, Synopsys verification suites