Perl, Verilog, Python, SV, Cadence or equivalent simulation tools, SV scripting languages

Usb, Pcie, Test Plans, Verification environments, Regression management, SoC ASIC Verification, Waveform tools, Uvm, systemverilog, Coverage-driven verification, RTL design concepts, Axi, Test benches, APB, AHB

Vcs, JIRA, Git, Bitbucket, Perl, Verilog, Python, Tcl, CVS, Gate-Level Simulation, Xcelium, Palladium, Uvm, systemverilog, Assertions, Zebu, Protium, Questa, RTL-to-Gate-Level Simulation, HAPS, SoC Verification

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

C, Spi, Shell, Verilog, I2c, System Verilog, Python, Uart, Can, Flexray, Perl, Ethernet, Cadence Tools, Xcelium, Uvm, UPF, GLS, safety simulator, VHDL, vManager, Formal applications, AMs, Axi, PSI5, APB, PAGLS, CPF, AHB

C, Verilog, Uvm

Performance Analysis, Linux drivers, workload characterization, systemverilog, CPU GPU benchmark characterization, performance analysis tools, SOC design verification, runtime, mobile SOC performance model development

Jtag, Pcie, Perl, Python, System Verilog, Tessent Embedded Analytics, UltraSoC, RISC Debug Architecture, UVM methodology, Design for Debug, High speed USB