Usb, Vcs, DDR, Perl, Pcie, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog, CXL, LPDDR, high-speed protocols

arm architecture , C, Ovm, Jtag, Perl, Verilog, Python, System Verilog, CPU architecture, interconnects, Uvm, power management techniques, debug architecture protocols, coherent fabrics, VHDL, SoC Verification, SVTB

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

C Programming, System Verilog, DSP Image RADAR processing, SOC Chip level Cluster Sub-System Verification, Interconnect NIC FlexNoC Cache Coherency, Uvm, Microcontroller and Microprocessor architecture, ARM Cores

C, Shell, Perl, Verilog, System Verilog, Python, Cadence Tools, Xcelium, Uvm, safety simulator, VHDL, vManager, Formal applications

DDR, Shell, Pcie, Perl, Python, JESD204B, Uvm, UPF, GLS, systemverilog, MIPI, Dft, USB3

Perl, Ovm, Vcs, Python, Tcl, Questa, Modelsim, Uvm, systemverilog

Regression Testing, Usb, Uart, C Programming, Ethernet, SVA, Functional Coverage, Uvm, UPF, Assertions, systemverilog, Axi, APB, AMBA Protocols, CPF, AHB, ARM-based SoC Verification

UFS (Universal Flash Storage), C, C++, Vcs, Makefile, Perl, Verilog, Ethernet, System Verilog, System Verilog verification language, Uvm, System Verilog assertion and coverage code, Synopsys VIPs, Waveform analyzer, Asic Design Verification, ASIC flow, Processor based SoC level verification, AXI-AMBA protocol variants, PCIe Protocol

C, Pcie, Perl, Python, Tcl, UFS, HSIO PHY Controllers, Skill, Open Verification Methodology, USB2, systemverilog, MIPI, USB3, Universal Verification Methodology