Soc Architecture, tessent DFT, DFT architecture definition, HDLs, Genus, Scan, Cadence digital implementation tools, Tempus, MBIST, JTAG boundary scan, ATPG flow implementation

Perl, Python, Logic design Architecture Verification, SV, DFT Engineering, Post Silicon Testing, IOBIST test-logic, coverage metrics, Profiling Tools, Uvm, constrained random testing

Unix, Report Automation, Svn, Git, Shell, Linux, Perl, Verilog, Python, Tcl, MBIST, log parsing, Scan compression, systemverilog, DFT fundamentals, TetraMax, Scan architecture, Synopsys DFT Compiler, flow orchestration, Cadence Modus, ATPG, LBIST, TestMAX

logic bist , boundary scan , simulation and verification flow, clock control block, DFT compression, silicon debug, DFT technologies, scan chains, fault modeling, DFT strategy and architecture, IP integration, DFT specification definition, DFT design and verification, DFT architecture, die level DFT validation, silicon bring-up, ASIC DFT synthesis, TAP controller

logic bist , static timing analysis, UNIX, Jtag, Linux, Perl, Verilog, Scripting Languages, Tcl, DFT techniques, Synthesis, Repair, Scan Insertion, memory BIST, equivalency checking, ATPG, EDA Tools, scan compression architecture, SSN Scan, IEEE standards, c-shell

logic bist , static timing analysis, UNIX, Jtag, Linux, Verilog, Synthesis, DFT techniques, Scan Insertion, memory BIST, equivalency checking, ATPG, EDA Tools, scan compression architecture, IEEE standards, SSN Scan

LBIST, MBIST, Synopsys, IST, simulation debug, low-power DFT methodologies, ATE bring-up, ATPG verification, DFT clocking strategies, SDC handling, DFT architecture SCAN, Low DPPM DFT, post-silicon debug, DFT timing closure, Sta, DFT architecture, Design For Testability, coverage improvement, IC Design Flow, DFT SCAN implementation, Siemens, scripting skills, Hierarchical DFT, Diagnosis flows