Perl, Verilog, Scripting Languages, Python, pinmuxing, Design Automation, chip level front-end design, Rtl Design, padring, SOC Assembly process, System-On-Chip design implementation flow, SOC integration

Verilog, power analysis, RTL

System Verilog, Verilog, power analysis, Debug, energy-efficient low power logic design, FPGA emulation, RTL Coding, silicon bring-up, Simulation, characterization

Verilog/SystemVerilog, Front-end quality checks, SoC integration, Low power optimization, ASIC RTL design

x86 assembly language , C, Perl, Ovm, Arm, Python, SVTB, CPU Architecture, Uvm, Power Management Verification

Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Synthesis, Asynchronous interface, SDCC, RTL Coding, Low power SoC design, micro-architecture, System-Verilog, SOC design, constraint development, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB

Vcs, Perl, Python, Tcl, Debugging methodologies, Verdi, Assertions SVA, Xcelium, Uvm, ASIC SoC Verification Flows, systemverilog, Coverage-driven verification, spyglass, Simulation and regression flows, Jenkins Regression Automation Tools, DVE, Questa, Functional Verification

Perforce, static timing analysis, Shell, Verilog, Version Control Systems, Scripting Languages, Python, Git, Perl, Tcl, cdc, Simulation, formal verification, EDA Tools, Rtl Design, Synthesis, SoC Architecture Design, LEC, AMBA protocols, systemverilog, Axi, APB, LINT, AHB, SoC Integration

redhawk , Tcl, Perl, VSLP, Synthesis, ICC, Logic equivalence checking, Low Power checking, Calibre, Power signal integrity, Physical Design Verification, SDC clean up, Place And Route, DRC, Physical Design, SOC design, Mixed signal block integration, Dc, Timing Closure, LVS, Pt, STA timing, Deep sub-micron designs, Formality, Manufacturability