Contribute as an ASIC RTL engineer to sub-system and chip-level integration activities, including task planning, hold code and design reviews, and contribute to sub-system/chip-level integration.
Interact closely with the architecture team and develop implementation strategies to meet quality, schedule, and power performance area for sub-system/chip-level integration.
Interact with the subsystem team and plan SOC milestones, plan quality checks as part of SOC milestones and guide subsystem teams with SOC level requirements (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.).
Work with the cross-functional team of verification, design for test, physical design,emulation, and software teams to make design decisions and represent project status throughout the development process.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
3 years of experience in RTL coding using Verilog or Systemverilog language.
Experience in high-performance design, multi-power domains with clocking.
Preferred qualifications:
Experience with multiple SoCs with silicon success.
Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).
Domain knowledge of one or more of the following: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, PinMux.
Understanding of cross-domain involving domain validation, design for testing, physical design, and software.
