Usb, Fpga, Perl, Pcie, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, Test Bench, transaction level modeling, AXI4

Usb, Jtag, Perl, Pcie, Ethernet, System Verilog, Python, UVM methodology, Design for Debug, scripting in Linux Unix environments, SoC architecture verification, TSN, ARM based SoC verification, High speed USB

Perl, Ruby, System Verilog, make, Uvm

Tcp, Pcie, Ethernet, System Verilog, RDMA, Data path verification performance tests, Building test benches, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Tcl Scripting, Python, System Verilog, HW–SW interaction, SoC TB architecture, test-plan creation, UPF-based methodologies, debug skills, UVM methodology, RTL integration, DV sign-off flows, gate-level simulation, power-aware verification

Tcp, Pcie, Ethernet, System Verilog, Forwarding logic Parsers P4, RDMA, Building test benches from scratch, System Verilog constraints structures and classes, Palladium, Verifying sophisticated blocks clusters and top level for ASIC, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

analog circuits , Fpga, Logic Design, Verilog, Sta, Scan Insertion, Power product design, Uvm, Synthesis scripts, ATPG generation, Regression frameworks, Synthesis, formal verification, Micro-architecture, ABV, RTL Coding, Timing Constraints, Functional Verification, System-Verilog, Digital Verification, Timing Analysis

Linux O.S., Arm Assembly, Perl, Networking Protocols, System Verilog, Python, Object-Oriented Design, Uvm, EDA Verification tools

Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, formal verification, MIPI, Test Bench, transaction level modeling, AXI4

C, Python, System Verilog, Systemc, AI enabled DV development, Uvm