power optimization , C, Linux, Perl, Unix Shell, Tcl, Advanced STA Concepts, Physical Design Flow, Block level PnR convergence, Timing Convergence, Cadence Innovus, LVS, PTSI Tempus, Physical Verification, formal verification, Timing Closure, DRC, PDN, Floor-planning, Place And Route, Synopsys ICC2

routing, PYTHON, Tcl, PERL, Noise analysis, LVS, Physical Verification, physical design methodology, Placement, Logic Synthesis, electro migration, power analysis, DRC, Clock Tree Synthesis

synopsys tools , Tcl Scripting, Asic Physical Design, place-and-route, IC Compiler, Timing Closure, Design Compiler, Fusion Compiler, sign-off, Power Planning, floorplanning

rc extraction , routing, Tempus, LVS, Cadence layout tools, Innovus, ERC, STA timing closure, DRC, Placement, Caliber tool, IR EM analysis, block level low power aware floorplanning, tape out activities, Clock Tree Synthesis

Computer Architecture, Verilog, Tcl, Python, Perl, Cadence Innovus, EDA Tools, digital logic, Physical Design, Methodology

Tcl, Python, Perl, Physical design verification, Physical Design, Synthesis2APR netlist, PPA optimization, CAD and physical design methodologies, Clock network guidelines, P R flow development, Logic equivalency RTL2Synthesis, Block-level place and route

congestion management , Tcl, Python, Perl, Synopsys ICC2, Cadence Innovus, clock gating, clocking methodologies, primetime, physical implementation, power-aware physical implementation, clock domain partitioning, SoC-level floorplanning, clock tree architecture, Timing Closure, low-power design techniques

Tcl, Python, floorplanning, Synthesis, Logical Equivalence, LVS, EDA Tools, Physical Verification, Budgeting, Timing Analysis, ERC, Place And Route, DRC, Clock CTS