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Physical design team is responsible for designing high performance microprocessor blocks for IBM Power and z mainframe servers.
. Responsible for high performance microprocessor blocks RTL to GDSII implementation
. Perform block level synthesis, floor-planning, placement and routing.
. Close the design to meet timing, power budget and area.
. Implement ECOs to address functional bugs and timing violations.
. Team player, with good problem solving and communication skills.
ABOUT IBM IBM's greatest invention is the IBMer. We believe that through the application of intelligence, reason and science, we can improve business, society and the human condition, bringing the power of an open hybrid cloud and AI strategy to life for our clients and partners around the world. Restlessly reinventing since 1911, we are not only one of the largest corporate organizations in the world, we're also one of the biggest technology and consulting employers, with many of the Fortune 50 companies relying on the IBM Cloud to run their business. At IBM, we pride ourselves on being an early adopter of artificial intelligence, quantum computing and blockchain. Now it's time for you to join us on our journey to being a responsible technology innovator and a force for good in the world. IBM is proud to be an equal-opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, gender, gender identity or expression, sexual orientation, national origin, caste, genetics, pregnancy, disability, neurodivergence, age, veteran status, or other characteristics. IBM is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Job ID: 115791021
Skills:
redhawk , primetime, PDN methodology, floorplanning, physical design implementation, STA constraints, Tempus, Cadence Innovus, IR EM mitigation, Physical Verification, Voltus, signoff tools, Synopsys ICC2
Skills:
power optimization , C, Linux, Perl, Unix Shell, Tcl, Advanced STA Concepts, Physical Design Flow, Block level PnR convergence, Timing Convergence, Cadence Innovus, LVS, PTSI Tempus, Physical Verification, formal verification, Timing Closure, DRC, PDN, Floor-planning, Place And Route, Synopsys ICC2
Skills:
synopsys tools , Tcl Scripting, Asic Physical Design, place-and-route, IC Compiler, Timing Closure, Design Compiler, Fusion Compiler, sign-off, Power Planning, floorplanning
Skills:
rc extraction , routing, Tempus, LVS, Cadence layout tools, Innovus, ERC, STA timing closure, DRC, Placement, Caliber tool, IR EM analysis, block level low power aware floorplanning, tape out activities, Clock Tree Synthesis
Skills:
PERL, Python, Tcl, Ir, Cadence, Mentor, LVS, EM Signoff, Synthesis, Formal Equivalence, DRC, Synopsys
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