Compressor-based scan chain insertion, Analog BIST implementation, DFT simulations

logic bist , Unix, Jtag, Linux, Perl, Tcl, Verilog RTL, silicon debug, memory and scan diagnostics, back-annotated gate level verification, Scan compression and insertion, ATPG, at-speed test, Memory BIST and repair scheme implementation, Fault Simulation, IJTAG

Constraints, Failure Analysis, physical design flow, Scan Insertion, silicon bring-up, DFT methodologies, Timing Analysis