power optimization , Perl, Scripting, Python, Tcl, Cadence, Mentor, Timing Analysis, Physical Design, Signal Integrity, EDA Tools, Synopsys

routing, block level place and route, floor-planning, Power grid analysis, Extraction, Physical Synthesis, Netlist, full chip implementation, GDS flow, STA timing, flow-automation, Signal Integrity, clock tree optimization, formal verification, Dft, Timing Constraints, Regression, digital design automation, Timing Closure, CTS IO timing, RTL-to-GDSII, Antenna fixing

Full chip, SOC design, Sub micron designs

Scripting, Physical Verification, Physical Design, PG creation, ESD latch-up, RDL knowledge, Innovus, floorplanning

PERL, Python, Tcl, Sta, CTS, Timing Convergence, ICC2, RTL2GDSII flow, Ir, Tempus, Block-level and Full-chip Floor-planning, primetime, Innovus, Synthesis, Physical Verification, Layout Closure, Physical Design, High Frequency Design Methodologies, Seahawk, Place And Route, ECO Timing Closure

DFT (Design for Testing), System Verilog, low power design, SOC design, Clock/Voltage Domain Crossing

Perl, automation, Python, Tcl, ASIC design flow, advanced physical design methodologies, Synthesis, RTL integration, scripting using Makefile, AI ML-driven optimization, modern EDA tools, Timing Closure, Verification, hierarchical physical design strategies, back-end physical design

Static Timing analysis, Perl, Tcl, Clock Planning, SoC designs, Power Plan, Digital place and route, Floor Planning, Clock Tree Synthesis, Parasitic Extraction, PnR Signoff