Tcp, Pcie, Ethernet, System Verilog, Forwarding logic Parsers P4, RDMA, Building test benches from scratch, System Verilog constraints structures and classes, Palladium, Verifying sophisticated blocks clusters and top level for ASIC, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

hardware engineering , Vcs, Perl, Python, Xcellium, NCSim, Uvm, UPF, systemverilog, Low power verification, Gate level simulation, VCFormal, Jaspergold, Questa, Functional Verification, Modelsim, formal verification

Vcs, Jenkins, Git, Pcie, Ethernet, Python, System Verilog, Tcl, Xcelium, SERDES, Uvm, GitLab CI, formal verification, Questa

bandwidth management , Microprocessor Cores, Specman E, hierarchical memory subsystems, Debug, interconnects, congestion control, SoCs, systemverilog, constrained-random verification environments, packet processing, Verification, standard IP components

Vcs, Git, Pcie, Ethernet, System Verilog, low-power verification techniques, cdc, Uvm, UPF, C Language, Axi, level shifter implementation, AMBA, FIFOs, APB, Questa, RISC-V CPU subsystems, clock reset architectures, power management strategies, AHB

Perl, Verilog, Python, Tcl, VHDL, Uvm, systemverilog

Coverage-driven methodologies, Debug techniques, systemverilog