static timing analysis, UNIX, Linux, Perl, Verilog, Tcl, CAD software scripts, Synthesis, DFT RTL integration, Scan Insertion, Timing Analysis, ATPG verification, waveform debugging tools, Rtl Design, EDA tools methodology, test pattern generation, DFT design-for-test, equivalency checking, DFD design-for-debug, verification of DFx logic, DFT documentation, c-shell

Jtag, Soc, Physical Design, Dft, ASIC, RTL