- Lead and define overall test chip architecture, including the functional and DFX aspects.
- Integrate high speed DDR PHY IPs into test chip top level RTL which requires working knowledge of DDR/LPDDR/HBM etc protocols.
- Develop additional custom logic at test chip top level for interfacing and interacting with PHY IPs and associated logic.
- Implementation of SOC DFT features (TAP controller, JTAG/IJTAG, GPIOs, ESD structures etc) into RTL.
- Gate level simulation using Synopsys VCS and Verdi.
- SOC-level SDC development and hand-off to PD
- UPF development and hand-off to PD.
- ATPG patterns translation from IP level to SOC level and hand-off.
- Spyglass bringup and analysis for scan readiness/test coverage gaps.
- Run all SOC RTL QA checks (Lint/CDC/RDC/VCLP etc)
- Support silicon bring-up and debug.
- Develop efficient DFx flows and methodology compatible with front end and physical design flows
EXPERIENCE & QUALIFICATIONS:
- BS/MS/PhD in EE/ECE/CE/CS with at least 10+ years of industry experience in SOC RTL/DFX execution with added exposure to high speed PHY or Serdes IPs design.
- Experience with the development of a complete TestChip RTL (including integration of IEEE1149.1 TAP, GPIOs etc) from early RTL design to post-silicon support.
- Exposure to MCM (multi-die integration into a package) would be desirable.
- Integration of several IPs (with or without integrated JTAG controllers) into the testchip environment.
- Experience with integration of PLLs and DFX care-abouts thereby.
- Test chip SOC level ICL/PDL transition and implementation.
- Understanding of STA fundamentals, experience with SDC development.
- Experience with UPF development.
- Experience with ATPG patterns translation from IP level to SOC level.
- Familiarity with SystemVerilog and UVM.
- Strong problem solving and debug skills across various levels of design hierarchies
