Usb, C, Makefile, Windows, Shell, Perl, Linux, Pcie, Verilog, Ethernet, Ruby, System Verilog, Systemc, IP level ASIC verification, acceleration HLS tools, Graphics pipeline knowledge, UVM testbenches, automating workflows in a distributed compute environment, AXI ACE Protocols, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools

Usb, C, Makefile, Windows, Shell, Linux, Pcie, Perl, Verilog, Ethernet, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, AXI ACE Protocols, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools

Test Plans, Nvme, DDR, Pcie, coverage analysis, UVM methodology, systemverilog, Axi, RTL debugging, testbenches, assertions, AHB

arm architecture , AI ML SoC exposure, Gate-Level Simulation, Cadence Tools, Arm Corestone, ATE pattern generation support, Test Bench Development, SystemVerilog UVM, ASIC SOC verification, Low-power verification experience, Functional Verification, AXI AHB APB Protocols

Assembly Language, C, Ovm, PERL, Verilog, Shell script, System Verilog, Systemc, System Verilog PLI, Uvm, Emulation, Functional Verification, DPI interface, SoC Verification

PERL, Verilog, Tcl, Uvm, systemverilog