Tcl, Python, Perl, routing, Synthesis, ASIC design flow, Timing Analysis, PPA optimization, EDA Tools, Placement, signoff, Timing Closure, RTL-to-GDSII

routing, Perl, Python, Tcl, ASIC design flow, Synthesis, Timing Analysis, signoff, EDA Tools, Timing Closure, Placement, PPA optimization, RTL-to-GDSII

Python, Mixed Signal