Physical Verification, Signoff checks, Timing Analysis, Timing constraint development, Digital Synthesis, DFT insertion, STA flow setup, RTL to Netlist Logical equivalence check, EM IR flows, Timing Noise DRC

rc extraction , C, Unix Shell, routing, PERL, Linux, Tcl, functional ECOs, Physical Design Flow, floorplanning, cross talk, timing optimization, low power implementation methods, Power Planning, Signal Integrity, formal verification, debugging timing violations, delay analysis, Placement, IR drop analysis, Clock Tree Synthesis

Sta, LINT, Synthesis, cdc, Dft, MMMC, primetime, Tempus, SDF generation, ETM Timing model generation

synopsys primetime , Tcl, Python, Perl, Cadence Tempus

PERL, Python, Tcl, Synthesis, Cadence

synopsys primetime , Debugging, Python, Perl, Tcl, OCV, timing closure techniques, latency, multicycle paths, derates, MMMC concepts, SDC timing exceptions, timing constraints development, POCV, ECO methodologies, clock uncertainty, Case Analysis, setup hold analysis, Cadence Tempus, clock tree, path-based analysis, jitter, false paths, Timing Closure, AOCV, skew

Timing Concepts, low-power design and multi-voltage domains, STA tools like Synopsys PrimeTime, synthesis and place route flows