static timing analysis, Perl, Python, Tcl, multi-clock domain designs, constraint development, STA tools, clock gating, Cadence synthesis tools, Timing Analysis, CPF-based power intent, multi-voltage domains, UPF, ECO flows, timing convergence, RTL-to-gate synthesis, Timing Closure, low-power design techniques, constraint validation

simics , Software Architecture, Computer Architecture, Python, System C, gem5, qemu, RISC-V architecture, Virtualizer

ECS, S3, Spring Boot, Java, Dynamodb, Microservices, Lambda, Typescript, AWS, Node.js, Graphql, Javascript, EKS

C Programming, ATS, Python, Git, Gerrit, SR-IOV, PCIe protocol expertise, BAR mapping strategies, HDM decoder programming, DMA engines, libSPDM, Linux auxiliary bus framework, MCTP, PASID

Cadence - Virtuoso, Tcl, Python, Perl, Spice Simulator, Synopsys, Uvm, SV, Mentor tools, Verilog-A, Verilog-D, Cadence, Verilog Hdl, Verilog-AMS, AMS simulation environment

Sql, Uat, Sit, Data Warehousing, Etl Testing, Python, Data Migration, Automation Frameworks, load validation techniques, mock loads, cutover plans, data lake architectures, structured project frameworks, data validation processes, data quality cleansing strategies

Nosql, Java, Restful Apis, Kubernetes, Python, Sql, Agentic AI, AI productivity tools, Go

Nosql, RDBMS, Gcp, AWS, Distributed Infrastructure Stack, Caching Strategies, Frontend Engineering Paradigms, Microservices Architecture, Distributed Queuing Systems, Cloud DevOps Practice, Generative AI Tools