C, Vcs, Perl, Verilog, Hardware Emulation Platforms, cdc, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification

Digital RTL Design, VHDL, Timing Analysis, Low-Power Design Techniques, Logic Synthesis, systemverilog

Python, Low power estimation, Timing Closure, Synthesis, RTL quality checks, ASIC Design, Electrical/Computer Engineering

pipelining , Debugging, Perl, Verilog, Python, Tcl, Analytical Skills, Reset architecture, Clock domain crossing CDC, Micro-Architecture, Linting, Digital Design Fundamentals, systemverilog, FSM design, Synthesis, RTL quality checks, RTL Coding, Low-power design methodologies, ASIC SOC design, Timing Concepts

Perforce, static timing analysis, Shell, Verilog, Version Control Systems, Scripting Languages, Python, Git, Perl, Tcl, cdc, Simulation, formal verification, EDA Tools, Rtl Design, Synthesis, SoC Architecture Design, LEC, AMBA protocols, systemverilog, Axi, APB, LINT, AHB, SoC Integration

Ovm, Shell Scripts, FPGA Design, Perl, Verilog, System Verilog, Python, Cadence Palladium, Synthesis, memory modelling, in-circuit emulation, Synopsys HAPS, emulation prototyping tools, Siemens Veloce, Uvm, AMBA Bus protocols, VHDL, simulation acceleration, STA timing closure, ZEBU, HDL simulation, Rtl Design

Network Security, DDR, Pcie, Ethernet, Static Timing Analysis, Arm, LINT, gate-level simulations, RTL implementation, cdc, mixed-mode simulations, RISC-V, Cadence, UPF techniques, systemverilog, RDC, tools such as Synopsys, design closure, Verification, Mentor Graphics