Digital RTL Design, VHDL, Timing Analysis, Low-Power Design Techniques, Logic Synthesis, systemverilog

System Verilog, Building test benches from scratch, ASIC verification using UVM

Unix, Python, Lsf, Bitbucket, Static timing analysis, AI ML, Jenkins, Git, Linux, Splunk, GenAI, cdc, Design Verification, design layout constraints, CI CD process, DesignSync, UPF, SDC, Dft, RDC, EDA Tools, Graph Neural Networks, Implementation, make, reinforcement learning, debug tools, convolutional Networks, Power-aware flows, Clocks, SW development

Tcp, Pcie, Ethernet, System Verilog, RDMA, Data path verification performance tests, Building test benches from scratch, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation

power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis

Tcp, System Verilog, Ethernet, Pcie, formal verification, Forwarding logic Parsers P4, Building test benches from scratch, RDMA, Zebu, System Verilog constraints structures and classes, HAPS, ASIC verification using UVM, Verifying sophisticated blocks clusters and top level for ASIC, Palladium, Veloce

Ecos, Tcl, Verilog, Python, DFT hooks, UPF, systemverilog, Ace, micro-architecture, low-power techniques, SVA, AHB, synthesis constraints, Timing Closure, APB, Axi, AMBA standard bus protocols