Shell scripting, Static Timing Analysis, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, Git, Dft, Synthesis, AXI-based interconnects, LINT, cdc, Sta, CXL, RDC

Digital RTL Design, VHDL, Timing Analysis, Logic Synthesis, Low-Power Design Techniques, systemverilog

UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

code coverage , Verilog, System Verilog, LINT, cdc, AXI protocol, Low power synthesis, Formality, SoC level Synthesis, UPF, Rtl Design, Synthesis, AMBA, Timing Analysis, RTL Coding, AHB, ip development, functional coverage, front-end design tools

multidimensional designs, project management, Design Verification, layout of complex integrated circuits, component and system simulation, Vlsi Design, Problem Solving, architecture and logic design

power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis

FPGA Design, Static Timing Analysis, Synthesis, Timing Closure, systemverilog, Code coverage analysis, RTL design using Verilog

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation

DDR, Pcie, Verilog, synthesis constraints, coherency memory subsystems, clock reset expertise, AMBA protocols, systemverilog, ECO flows, performance power analysis, Dft, ASIC RTL, cross-team collaboration, security blocks, low-power design, micro-architecture, SVA

System Verilog, Tcp, Pcie, Ethernet, Building test benches from scratch, ASIC verification using UVM, Gate Level Simulations, Forwarding logic Parsers P4, RDMA, Zebu, Veloce, Palladium, HAPS, formal verification