power integrity , Tcl, Python, Perl, Debugging, Static Timing Verification, Power Integrity Analysis, Automation Scripts, Physical Verification, Timing ECO Implementation, Equivalence Checks, Physical Design, Physical Design Verification, formal verification, Timing Closure, CTS Strategies, Hierarchical Floor Planning

power optimization , Static Timing Analysis, Rtl Design, Physical Verification, DRC/LVS Checks, floorplanning, Place And Route, Signal Integrity, Timing Closure, Layout Optimization