Vcs, DDR, Pcie, Usb, Ethernet, CHI, Xcelium, Uvm, UPF, coverage-driven verification, VIP integration and customization, LPDDR, low-power verification, Ace, Emulation, debug using industry-standard simulators, systemverilog, FPGA prototyping, constrained random methodology, Axi, AMBA, APB, Questa, CXL, CPF, IP and SoC level verification, AHB, high-speed protocols, SVA

Shell, C, Verilog, Python, Uvm, systemverilog

C, Verilog, System Verilog, AI tools, SoC UPF power aware verification, Uvm, DFx DFT infrastructure functional verification

Soc, C++, Pcie, Sata, Firmware, Test Planning, Uvm

Vcs, JIRA, Git, Bitbucket, Perl, Verilog, Python, Tcl, CVS, Gate-Level Simulation, Xcelium, Palladium, Uvm, systemverilog, Assertions, Zebu, Protium, Questa, RTL-to-Gate-Level Simulation, HAPS, SoC Verification

Ovm, Pcie, Verilog, Ethernet, System Verilog, power management flows, Uvm, HSIO, Low Power Verification, RTL GLS level simulations, SOC bot flow, System Verilog Assertions

System Verilog, SoC Verification, Rtl Design, Design Verification, Uvm, Asic verification