Verilog, power analysis, RTL

System Verilog, Verilog, power analysis, Debug, energy-efficient low power logic design, FPGA emulation, RTL Coding, silicon bring-up, Simulation, characterization

Verilog/SystemVerilog, Front-end quality checks, SoC integration, Low power optimization, ASIC RTL design

Vcs, Perl, Python, Tcl, Debugging methodologies, Verdi, Assertions SVA, Xcelium, Uvm, ASIC SoC Verification Flows, systemverilog, Coverage-driven verification, spyglass, Simulation and regression flows, Jenkins Regression Automation Tools, DVE, Questa, Functional Verification

Perforce, static timing analysis, Shell, Verilog, Version Control Systems, Scripting Languages, Python, Git, Perl, Tcl, cdc, Simulation, formal verification, EDA Tools, Rtl Design, Synthesis, SoC Architecture Design, LEC, AMBA protocols, systemverilog, Axi, APB, LINT, AHB, SoC Integration

Computer Architecture, reset methodologies, Timing Constraints, Microarchitecture, digital RTL design