Pcie, Perl, Verilog, Python, System Verilog, Tcl, CXL

arm architecture , C, Python, System Verilog, verification methodologies and tools, CPU microarchitecture verification

Verilog, System Verilog, CPU architecture, Coherent fabric designs, debugging skills, ARM knowledge

Vcs, Perl, Python, Tcl, Debugging methodologies, Verdi, Assertions SVA, Xcelium, Uvm, ASIC SoC Verification Flows, systemverilog, Coverage-driven verification, spyglass, Simulation and regression flows, Jenkins Regression Automation Tools, DVE, Questa, Functional Verification

Shell, Perl, Vcs, Python, Xcelium, QuestaSim, Uvm, systemverilog

Python, Verilog, Unix, System Verilog, Perl, Linux, VHDL

System Verilog, low-power design verification, Uvm

Visual Studio Code, System Verilog, GitHub Copilot, Mixed-Signal verification, Hspice, Uvm, Cadence Xcelium-AMS, Spectre