static timing analysis, Verilog, Synthesis, Design Reviews, SoC debug architecture, SoC integration, DFT concepts, formal verification tools, ARM coresight components, systemverilog, Rtl Design, Simulators, formal verification, constraints timing analysis, Optimization Techniques, Verification, APB protocol

pipelining , Debugging, Perl, Verilog, Python, Tcl, Analytical Skills, Reset architecture, Clock domain crossing CDC, Micro-Architecture, Linting, Digital Design Fundamentals, systemverilog, FSM design, Synthesis, RTL quality checks, RTL Coding, Low-power design methodologies, ASIC SOC design, Timing Concepts

FPGA-SoC interfacing, Python Perl, Peripheral interfaces SPI I2C UART DDR4, Xilinx FPGA design and prototyping, AMBA protocols AXI AHB APB, Protocol analyzers SPI CAN Ethernet, Hardware debugging tools Oscilloscope Logic Analyzer, Micro-architecture definition and logic design, Implementation of DSP algorithms on FPGA Radar EW systems, RTL Design using Verilog VHDL, Constraints development linting CDC analysis, Simulation and verification methodologies, FPGA synthesis implementation and timing closure, High-speed interfaces PCIe Ethernet JESD204B C

Git, Verilog, System Verilog, Rtl Design, microarchitecture development, cdc, interconnect logic, FIFOs, clock reset architectures, low-power design techniques, SDC and UPF constraint writing

Usb, Soc Architecture, DDR, Pcie, Verilog, Ethernet, System Verilog, Sta, LINT, Synthesis, cdc, UCIe, spyglass, RDC, VHDL, formal checking

Usb, Soc Architecture, DDR, Pcie, Verilog, Ethernet, System Verilog, LINT, Sta, Synthesis, cdc, UCIe, VHDL, formal checking, RDC

Unit Testing, Performance, Verilog, Synthesis, cdc, post-silicon validation, design documentation, code reviews, power-related issues, systemverilog, LINT, silicon bring-up, Power, block-level design integration, design optimization

Vcs, DDR, Verilog, Digital Signal Processing, Synthesis, RTL simulation, neural network accelerators, STA tools, floating-point computation, Sram, systemverilog, Rtl Design, Axi, motion control systems, linting, Modelsim, AHB

static timing analysis, Verilog, VHDL, Synopsys VCS, Uvm, SDC Standard Delay Constraint, Modelsim, Cadence Incisive, Rtl Design