Area and power-efficient complex RTL design, High performance low latency high bandwidth design techniques, Low power microarchitecture techniques, Experience with simulators and waveform debug tools, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications

Cache, Soc Architecture, Perl, Verilog, Python, power analysis, Synthesis, memory compression, FPGA design verification, systemverilog, digital logic design principles, logic synthesis techniques, RTL design concepts, Dft, FPGA and emulation platforms, fabric coherence, DRAM, low-power design techniques, assertion-based formal verification

Ecos, Tcl, Verilog, Python, DFT hooks, UPF, systemverilog, Ace, micro-architecture, low-power techniques, SVA, AHB, synthesis constraints, Timing Closure, APB, Axi, AMBA standard bus protocols

Bus Protocols (AHB/AXI/NOC), low power design, formal verification, Verilog/SystemVerilog, Spyglass CDC/Lint, Rtl Design

Verification methodology., IP design verification, Functional coverage, systemverilog, LINT, ARM SoCs, Rtl Design