Uart, python, Debugging, SV, test cases coding, Uvm, Test bench development, IJTAG, APB, Code and Functional coverage analysis, Axi, BUS Protocols

System Verilog, Coverage models, DV methodology, Testbench design, Uvm

simvision , Perl, Python, FineSim, Xcelium, UVM-based verification methodologies, WaveView, DRAM memory architecture, systemverilog, SpectreFx, Hspice, FastSpice tools, PrimeSim, virtuoso