Arm, C, verification methodologies, Uvm, RISCV, functional coverage, Verification Tools, DSP core

arm architecture , Verification tools for simulation and debug, Verification methodologies, UVM-based verification test benches, UVM methodology, Bus functional models, Functional coverage, formal verification

Tcl, Verilog, Python, Shell, Git, VHDL, Uvm, Xilinx Vivado, systemverilog, Xcelium

Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Verdi, IUS, UVM environments, SystemVerilog UVM, GLS, coverage closure, debug tools, testbench architecture, Axi, IP SOC verification, Questa, CXL, CPU-based verification

Ovm, Verilog, Database Management, Uvm, Synopsys VCS, Cadence IES, Cadence Jasper, Metric-driven verification, Regression management, Calibration board skew and jitter modeling, Verification techniques, Contention checking, silicon debug, Debug environments, Simulation Tools, Memory controller protocols, Power verification, Reset verification, Gate level simulation, Formal property checking tools, Verification management tools, Verification methodology, High speed interface verification

Linux, Perl, Python, Tcl, Synopsys Custom Compiler, Layout automation, VoltusXFA, Calibre, Skill, Totem, Physical Verification, Pulsic Unity Itools, PDN analysis tools, Cadence Virtuoso, ICV

Usb, C, C++, Debugging, Test Plan, Object Oriented Programming, Writing Test Cases, Oop, DDR, Ethernet, Pcie, Perl, Tcl, Function coverage, Coverage driven verification, Uvm, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, CXL, Test bench development, Simulation, System-Verilog

Shell, C, Perl, Python, Tcl, Uvm, systemverilog

C DPI Development, Hardware-Software Integration, Debugging Expertise, Scripting and Automation, Verification Planning, Uvm, systemverilog, SoC Verification, Coverage-Driven Verification