Jasper, Perl, Verilog, Python, Tcl, Xcelium, Memory Test methodologies, Modus, Scan Insertion, VHDL, ATPG, Genus

Soc Architecture, tessent DFT, DFT architecture definition, HDLs, Genus, Scan, Cadence digital implementation tools, Tempus, MBIST, JTAG boundary scan, ATPG flow implementation

Perl, Logic Design, Python, DFT Engineering, SV, Post Silicon Testing, Coverage metrics, Constrained random testing, Uvm, Profiling Tools, Architecture Verification

Perl, Python, Logic design Architecture Verification, SV, DFT Engineering, Post Silicon Testing, IOBIST test-logic, coverage metrics, Profiling Tools, Uvm, constrained random testing

boundary scan , Perl, Python, Tcl, test techniques, pattern retargeting, Scan Insertion, STA constraint delivery, advanced DFT features, MBIST, IP integration, SSN, ATPG simulations, IEEE 1500, Dft, Gate-Level DFT verification, pattern generation, LBIST, debugging techniques, Compression, IJTAG

Unix, Report Automation, Svn, Git, Shell, Linux, Perl, Verilog, Python, Tcl, MBIST, log parsing, Scan compression, systemverilog, DFT fundamentals, TetraMax, Scan architecture, Synopsys DFT Compiler, flow orchestration, Cadence Modus, ATPG, LBIST, TestMAX

Verilog, Jtag, Dft, MBIST, IEEE1500, IEEE1687, ATPG, Cadence