Verilog, advanced stimulus generation techniques, Uvm, coverage-driven verification, systemverilog

analog circuits , Fpga, Logic Design, Verilog, Sta, Scan Insertion, Power product design, Uvm, Synthesis scripts, ATPG generation, Regression frameworks, Synthesis, formal verification, Micro-architecture, ABV, RTL Coding, Timing Constraints, Functional Verification, System-Verilog, Digital Verification, Timing Analysis

Pcie, Nvme, DDR, UVM-based SV test-benches, CPU sub-systems, quality metrics, verification methodologies, NAND

DDR, Pcie, Uart, I2c, Axi, IP verification, FPGA-based verification, APB, Uvm, C-based tests, systemverilog

C, Python, AI-assisted development tools, emulation or FPGA-based verification, Uvm, systemverilog

code coverage , System Verilog, Cover groups, Functional coverage, Assertions, DDR4, Uvm, DIMM, DDR5

bandwidth management , Microprocessor Cores, interconnects, standard IP components, systemverilog, hierarchical memory subsystems, Specman E, constrained-random verification, Verification, IP subsystem SoCs, packet processing, congestion control, Debug

AMBA5 protocols (AXI5/ACE5/CHI), Cache coherency protocols (CHI, CXL), SystemVerilog UVM-based testbench development, Ace, CCIX, Functional coverage

Python, System Verilog, Uvm, Gate Simulation, Coverage Closure, Asic verification