Tcp Ip, Pcie, Perl, Shell scripting, Ethernet, RDMA IPs, VCS simulation tool, Silicon IP development process methodologies, networking IP solutions, Verilog RTL design, Design for Test methodologies, DMAs, NVMe based Storage IP

Verilog, Asynchronous interface, Synthesis, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Multi Clock designs, System-Verilog, formal verification

static timing analysis, Verilog, Debugging, Integration, Synthesis, multi-clock domain architectures, digital design fundamentals, power optimization techniques, low-power design methodologies, micro-architecture development, Physical Design, systemverilog, Dft, Axi, APB, Timing Closure, RTL Coding, Verification, AHB

Debugging, System Verilog, Sta, Synthesis, Wi-Fi, FPGA RTL design, Uvm, DSP fundamentals, Wireless Communication, 5G, VHDL, high-speed packet processing, AMD Zynq RFSoC, Timing Closure, 5G LTE, Altera Agilex

Perl, Verilog, Shell scripting, LINT, cdc, Connectivity, RTL quality checks, SOC design, VCLP

Perl, Verilog, Shell scripting, LINT, cdc, RTL quality checks, Connectivity, SOC design, VCLP

Shell scripting, Tcp Ip, Ethernet, Pcie, Perl, DMAs, Design for Test methodologies, NVMe based Storage IP, Verilog RTL design, RDMA IPs, VCS simulation tool, Silicon IP development process methodologies

analog circuits , C, Perl, Verilog, Python, AI tools, Vlsi, WREAL, statistical and data analysis tools, bench testing equipment, Jmp, Rtl Design, mixed-signal VLSI, Yield3, assembly level programming, digital logic, Verilog-AMS, Flash memory architecture