Calibre, Analog Layout, Cadence Virtuoso XL, Design for Manufacturability Principles, Signal Integrity Analysis, Power Distribution Techniques

scripting expertise, Cadence LVS, Calibre physical verification flow, layout XL, EXL, Cadence Virtuoso, layout design and verification tools, GXL

fast simulation tools and waveform viewers, deep submicron technology challenges, NMDL and CCST libraries, writing SPICE decks stimulus and test vectors, FinFET technology, layout impact on speed capacitance power and area, generating libraries and performing QA sign-off, layout parasitic extraction, memory architectures and performance optimization, LVS DRC debugging skills and verification for lower technology nodes, memory leafcell layout design, EDA tools including Cadence SKILL scripting and automation for compiler flows and layout reuse

Perl, Logic Design, Python, SV, DFT Engineering, Post Silicon Testing, Coverage metrics, Constrained random testing, Uvm, Profiling Tools, Architecture Verification

remediation , Intune, Excel, SCCM, SLA KPI-driven global operations, Powerpoint, Active Directory, Utilization monitoring, CMDB processes, Optimization automation, Reporting and monitoring platforms, Software deployment tools, Antivirus management consoles, Vulnerability management processes, Unused asset recovery, License Manager for ELP reporting, Physical stock verification

FPGA-SoC interfacing, Python Perl, Peripheral interfaces SPI I2C UART DDR4, Xilinx FPGA design and prototyping, AMBA protocols AXI AHB APB, Protocol analyzers SPI CAN Ethernet, Hardware debugging tools Oscilloscope Logic Analyzer, Micro-architecture definition and logic design, Implementation of DSP algorithms on FPGA Radar EW systems, RTL Design using Verilog VHDL, Constraints development linting CDC analysis, Simulation and verification methodologies, FPGA synthesis implementation and timing closure, High-speed interfaces PCIe Ethernet JESD204B C

Unix, Linux, Perl, Shell scripting, Python, Tcl, Place Route Cadence Innovus, Physical Verification Calibre DRC LVS, IR EM Cadence Voltus RedHawk, STA Cadence Tempus

redhawk , Shell, Python, Tcl, SC CADENCE, PDK collateral development, semiconductor device physics, Voltus, Calibre, EDA Tools, EMIR tool flows, Reliability verification, SVRF, ESD PERC design rules

Usb, DDR, Shell, Perl, Ethernet, Python, Emulation, UVM methodology, high-speed interfaces PCIe, systemverilog, scoreboards, industry-standard simulators and tools, formal verification, ASIC SoC architecture, functional coverage assertions, debugging skills, low-power verification UPF, SVA