simvision , Perl, Shell scripting, Python, Tcl, Xcelium, VIVA, VerilogAMS, Virtuoso ADE Assembler, SV RNM, System Verilog UVM, Regression flows

automation, Scripting, SoCs, Real model creation, mixed signal verification fundamentals, PSL SV assertions development, model validation, VerilogA, SV Verilog, environment development, verification planning, Verilog-AMS, verification of Power management IPs, behavioral modelling of analog blocks

SystemVerilog (SV), Vcs, Perl, Python, Tcl, AMS verification, Xcelium, Skill, Verilog Hdl, behavioral modeling, Cadence Xcelium + Spectre, Synopsys XA-VCS, Mentor Eldo ADMS, UVM testbench development, Rtl Design, Mixed-signal simulation environments, Verilog-D, VerilogAMS, Verilog-A