Visual Studio Code, System Verilog, GitHub Copilot, Mixed-Signal verification, Hspice, Uvm, Cadence Xcelium-AMS, Spectre

Mixed-Signal DV, AMS Verification, Analog Modeling, systemverilog, behavioral modeling, Chip Verification

analog circuits , Unix Environment, DDR, shell scripting, Verilog, Python, Models, memory subsystems, digital design processes, simulation debugging, RTL, Uvm, top-level integration, systemverilog, Schematics, VerilogAMS

Register modeling, coverage analysis, firmware interaction, regression management, SERDES, Uvm, systemverilog, PHY architectures