Dac, Pll, Mixed-signal IC design, Sigma-Delta ADC, Op-amp, Spectre simulation, Analog IC design, Spice, Cadence toolset, IC CAD tools, Signal Processing

low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks

Perl, Python, Tcl, Sta, CTS, pegasus, floorplanning, Cadence Toolchain, Power Grid, Tempus STA, Innovus, Calibre, MMMC, Timing Closure, Sign-off, ECO generation, SI crosstalk analysis, GDSII

low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks

redhawk , Python, Routing, Apache, Perl, Tcl, physical design methodologies, floor-planning, CTS, LVS, PPA tradeoffs, Calibre, Physical Verification, Extraction, StarRC, Synopsys fusion compiler, floor plan synthesis, Synthesis, CPU physical design, EM, Ir, signoff, Place And Route, Timing Closure, DRC, Placement, Cadence PrimeTime

Synopsys VCS, High Speed Serial Interfaces, Cadence Incisive, IP verification, Coverage Closure, Interconnect Protocols, Uvm, systemverilog

Shell, Perl, Python, Tcl, Ecos, Flows, automation, Innovus, primetime, ICC2, Tempus, FusionCompiler, Design Reviews, EM closure, Ir, PD methodologies, tapeout readiness, RTL-to-GDSII flow, Timing Closure, Si, PPA optimization