power analysis, DDR testing methodologies, verification flow, debug validation, STA simulation, IR-drop mitigation, spyglass, Ate, Dft, Tessent, SERDES, patterns generation, Timing Closure, silicon bring-up, ASIC DFT synthesis, Synopsys

Shell, Perl, Python, Tcl, advanced Design languages, SOC IP Integration, Rtl Design

C, Vcs, Perl, Verilog, Hardware Emulation Platforms, cdc, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, ASIC Design, Veloce, formal verification

PERL, Tcl, STA tools, physical verification tools, Cadence Innovus, synthesis Place and Route workflows

low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks

post layout parasitic extraction, Monte Carlo analysis, integrated power converters, bandgaps, block level topology selection, Spectre, Cadence tool set, switching regulators, schematic generation, DACs, VHDL, charge pumps, Amplifiers, PMICs, Spice, mixed-signal IC design, Analog Design, Comparators, IC CAD tools, precision analog control

low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks