power integrity , Pvs, Static Timing Analysis, Python, Tcl, primetime, ICC2, Cadence Innovus, Synopsys Fusion Compiler, LVS, Dfm, Calibre, Physical Verification, StarRC, UCIe PHY Integration, Antenna, floorplanning, EM, IR-drop, Place-and-Route, Thermal-aware Placement, Physical Design, ERC, Timing Closure, DRC

Scripting Language, python, Program Analysis, Verilog, Computer Architecture, benchmark characterization, Benchmarking, workloads characterization, microarchitectural timing simulator, x86 assembly language programming, VHDL, Bottleneck Analysis, hardware performance counters

routing, floorplanning, physical optimization, LVS, physical ECO implementation, Cadence Innovus, congestion analysis, Physical Verification, sign-off, Placement, IR drop, Calibre, antenna checks, Physical Design, primetime, Synopsys ICC2, Timing Closure, ERC, DRC, Power Planning, RTL-to-GDSII, StarRC

power integrity , Chip-Package Co-Design, Physical Design, floorplanning, Bump Planning, Package Interface Design, Signal Integrity, EDA Tools, Package Design

Dac, Op-amp, Sigma-Delta ADC, Signal Processing, Spectre simulation, Analog IC design, IC CAD tools, Spice, Pll, Mixed-signal IC design, Cadence toolset

Python Scripting, Perl, Verilog, Static timing analysis, Tcl, Synthesis P and R tools, Spice simulations and analysis, Memory post silicon analysis

Usb, Mac, Perl, Pcie, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Synopsys - ICC, Shell scripting, Tcl, Routing, Perl, Power grid analysis, Timing Closure, Place and Route tools, Antenna fixing, Floorplan, DRC-LVS closure, Signal Integrity, Placement, Physical Design, Cadence – Innovus Encounter